An OpenCL-based parallel acceleration of aSobel edge detection algorithm Using IntelFPGA technology

An OpenCL-based parallel acceleration of aSobel edge detection algorithm Using IntelFPGA technology

Blog Article

This paper examines the feasibility of using commercial out-of-the-box Reconfigurable Field Programmable Gate Array (FPGA) technology and the OpenCL framework to create efficient Sobel edge-detection implementation, which is considered a fundamental part in the field of image aluminum lotion and video processing.The revised proposed approach was created at a high level of abstraction and executed on high commodity Intel FPGA platform.This was performed in a manner that was designed to allow the high-level compiler/synthesis tool to manipulate a task a parallelism model.

The most promising FPGA and the naive implementations were compared to their single-core CPU software equivalents while manipulating local-memory, pipelining, loop unrolling, vectorization, internal channels mechanisms and memory coalescing to provide a much more effective hardware design.The run-time and the power consumption attributes were estimated for each implementation.The proposed FPGA based 3 piece horse wall art implementations were found to have significantly better runtime and power consumption with approximately up to 37 folds of improvement in the whole execution/transfer time, and up to 53 folds of improvement in energy consumption when compared to a specific single-core CPU based implementation.